library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity counterC is
  port( 							
    clk, reset: in std_logic;
    i_read_L: in std_logic;
    o_snd_L:  out std_logic; --o_hold, 
    i_FIFO_L: in std_logic_vector(11 downto 0);
    i_count: in std_logic_vector(11 downto 0); --receives max count from Fifo Monitor
    o_count:  out std_logic_vector(11 downto 0);
    en_test: out std_logic   --, reset_test
    );
end counterC;

architecture behavior of counterC is  

component counterB
	PORT
	(
		clk_en		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (11 DOWNTO 0);
		sclr		: IN STD_LOGIC ;
		sload		: IN STD_LOGIC ;
		q			: OUT STD_LOGIC_VECTOR (11 DOWNTO 0)
	);
end component;	
	
	signal s_en, s_snd_L: std_logic; -- s_hold, s_reset, 
	signal s_count: std_logic_vector(11 downto 0);	
--	logic

begin

 process (reset, i_read_L, i_FIFO_l,  s_en, s_count, i_count)
 begin
	if reset = '1' then 
		s_snd_L <= '0';
		s_en	<='0';
	end if;
	if i_read_L = '1' then
		s_snd_L <= '0';
		s_en	<= 	'1';
	end if;	
	if s_count = i_count then 
		s_snd_L <= 	'0'; 
		s_en 	<= 	'0';
	elsif s_count = i_count -1 then 
		s_snd_L <= '1';
		s_en <= '1';
	else
		s_snd_L <= '0';
		s_en <= '1';
	end if;	
end process;

	counterB_inst: counterB
	Port Map (
		clk_en 	=> s_en, 
		clock 	=> clk,	
		data 	=> x"000",
		sclr 	=> reset or i_read_L, 
		sload 	=> i_read_L,	
		q 		=> s_count
		);
		
--output logic
	o_snd_L <= s_snd_L;	
	o_count <= s_count;
	en_test<= s_en;

end behavior;
	